82551QM Datasheet, PDF (68/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
9.2.3
Modem Status Register
The Modem Status field is a 16-bit word register. It provides basic track of CardBus related events.
All bits are cleared by RST#.
Table 24. Modem Status Register
Bits Default Read/Write
Description
15
14
13:11
10:9
8
7
6:5
4
3:0
0
0
000
01
0
0
00
1
0000
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Parity Error.
System Error Enable.
Signaled/Received Target Abort.
Device Select Timing.
Data Parity Detect.
Fast Back-to-Back Capable.
Reserved. These bits are reserved and should be set to 00b.
New Capability.
Reserved. These bits are reserved and should be set to 0000b.
9.2.4
Modem Revision ID Register
The Modem Revision ID register is a Dword, read only field. It is composed of the Revision ID
byte and a 24-bit Class Code register. Its value is loaded from the EEPROM. The Class Code
identifies the function as a modem. The Class Code and Revision ID are listed in Table 25.
Table 25. Modem Revision Register
Bits
31:24
23:16
15:8
7:0
Default
07h
00h
02h
XXH
Read/Write
Description
Read Only
Read Only
Read Only
Read Only
Base Class. This indicates that the 82551QM is a communication
device.
Subclass. This indicates the serial controller equals 00h.
Program Interface. This indicates that the 82551QM is 16550 UART
compatible and initialized by EEPROM word FEh.
Revision Number. This indicates the revision number and is initialized
by EEPROM word FEh.
9.2.5
Modem Header Type Register
The Modem Header Type field is a byte wide, read only register. It indicates that this is a
multifunction card and a value of 80h is hard-coded in the silicon.
9.2.6
Modem I/O Base Address Register
The Modem I/O BAR is a Dword register that specifies the I/O base address for accessing the
82551QM’s modem. The required I/O space is 8 bytes.
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Datasheet