82551QM Datasheet, PDF (77/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

Networking Silicon — 82551QM
These CardBus registers are used by software to determine which event has occurred, to manage
the event, and to control the CSTSCHG signal.
The 82551QM supports only the interrupt and general wake-up event bits in the card status change
registers¹. These registers complement the PCI Power Management registers in a non-ACPI
compliant OS. They are initialized by a power-up reset on the ALTRST# pin.
The location of these registers should be specified within the configuration space pointing to offset
address 30h of the CSR.
Note: Access to the CSTSCHG registers in PCI mode is not allowed.
10.1.13.1 LAN Function Event Register
The Function Event register specified the event that changed the status.
Table 33. LAN Function Event Register
Bits Function Default
Description
31:16 Reserved 0
15
INTR
0b
14:5 Reserved 0
4
GWAKE 0b
3
Reserved 0b
2
Reserved 0b
1
Reserved 0b
0
Reserved 0b
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for as the interrupt bit. It is set when the Ethernet
interrupt source is set, regardless of the mask value. It is cleared when
the OS writes 1b to this field and the interrupt source has been
serviced. Writing 0b to this field has no effect.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. It is set when the Ethernet wake-
up source is set, regardless of the mask value. Writing 1b to this field
clears this bit and the PME Status bit in the PMCSR. Writing 0b to this
field has no effect. Note that writing 1b to the PME Status bit in the
PMCSR has the same effect.
Bit 3 is reserved in the CardBus Specification.
Reserved.
Reserved.
Bit 0 is reserved in the CardBus Specification.
1. For a combination LAN/modem card, the 82551QM implements two independent sets of card status change registers. Each set controls its
function separately.
Datasheet
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