82551QM Datasheet, PDF (76/120 Pages) Intel Corporation – Fast Ethernet Multifunction PCI/CardBus Controller

82551QM — Networking Silicon
Note: The PMDR is initialized at ALTRST# reset only.
10.1.11 General Control Register
The General Control register is a byte register and is described below. The General Control register
is used in CardBus mode only.
Table 31. General Control Register
Bits
7:2
1
0
Default
000000b
0b
0b
Read/Write
Description
Read Only Reserved. These bits are reserved and should be set to 000000b.
Read/Write
Read/Write
Deep Power-Down on Link Down Enable. If a 1b is written to this
field, the 82551QM may enter a deep power-down state (sub-3 mA) in
the D2 and D3 power states while the link is down.
In this state, the 82551QM does not keep link integrity. This state is not
supported for point-to-point connection of two end stations.
Clock Run Signal Disable. If this bit is set to 1b, then the 82551QM
always requests the PCI clock signal. This mode can be used to
overcome potential receive overruns caused by Clock Run signal
latencies over 5 µs.
10.1.12 General Status Register
The General Status register is used in CardBus mode only and is a byte register that indicates the
link status of the 82551QM.
Table 32. General Status Register
Bits
7:3
2
1
0
Default
00000b
--
--
0b
Read/Write
Description
Read Only Reserved. These bits are reserved and should be set to 00000b.
Read Only
Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b)
or half duplex (0b).
Read Only
Read Only
Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps
(0b).
Link Status Indication. This bit indicates the status of the link: valid
(1b) or invalid (0b).
10.1.13
Ethernet Card Status Change Registers
The PME signal used in PCI systems is replaced by the Card Status Change (CSTSCHG) signal in
CardBus systems. The CardBus specification requires the use of control/status registers related to
CSTSCHG. There are four event related registers.
1. Function Event Register: Specifies the event that changed status
2. Function Event Mask Register: Masks CSTSCHG signal assertion for specified events
3. Function Present State Register: Reflects the current state of each condition that may cause a
status change or interrupt
4. Force Event Register: Simulates status change events for troubleshooting purposes
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Datasheet