243658-020 Datasheet, PDF (59/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
3.3.3
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10 percent of the total signal swing (V_HI – V_LO)
above and below its final value. A signal should be within the settling limits of its final value, when
either in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
3.4
AGTL+ Signal Quality Specifications and Measurement
Guidelines (FC-PGA/FC-PGA2 Packages)
3.4.1
Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely result of
excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and overshoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the FC-PGA/FC-PGA2 processor performance, care must be taken
to ensure that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also
contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer
model will impact results and may yield excessive overshoot/undershoot.
3.4.2
Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)
Magnitude describes the maximum potential difference between a signal and its voltage reference
level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS
using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to
VTT. This can be accomplished by simultaneously measuring the VTT plane while measuring the
signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform using a
Math function where the Signal waveform is subtracted from the VTT waveform. The true
undershoot waveform can also be obtained with the following oscilloscope data file analysis:
Converted Undershoot Waveform = VTT– Signal_measured
Note: The converted undershoot waveform appears as a positive (overshoot) signal.
Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determined independently.
Datasheet
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