243658-020 Datasheet, PDF (46/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins
(for Both S.E.P. and PPGA Packages)
T# Parameter
T30: TCK Frequency
T31: TCK Period
T32: TCK High Time
T33: TCK Low Time
T34: TCK Rise Time
T35: TCK Fall Time
T36: TRST# Pulse Width
T37: TDI, TMS Setup Time
T38: TDI, TMS Hold Time
T39: TDO Valid Delay
T40: TDO Float Delay
T41: All Non-Test Outputs Valid Delay
T42: All Non-Test Inputs Setup Time
T43: All Non-Test Inputs Setup Time
T44: All Non-Test Inputs Hold Time
Min
Max
Unit Figure
Notes
16.667 MHz
60.0
ns
25.0
ns
25.0
ns
5.0
ns
5.0
ns
40.0
ns
5.0
ns
14.0
ns
1.0
10.0
ns
25.0
ns
2.0
25.0
ns
25.0
ns
5.0
ns
13.0
ns
3
3
@1.7 V; 10
3
@0.7 V; 10
3
(0.7 V–1.7 V); 4, 10
3
(1.7 V–0.7 V)^; 4, 10
6
Asynchronous; 10
9
5
9
5
9
6, 7
9
6, 7, 10
9
6, 8, 9
9
6, 8, 9, 10
9
5, 8, 9
9
5, 8, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. For the S.E.P. and PPGA packages: All AC timings for the TAP signals are referenced to the TCK rising edge
at 1.25 V at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the
processor core pins.
For the FC-PGA/FC-PGA2 packages: All AC timings for the TAP signals are referenced to the TCK rising
edge at 0.75 V at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the
processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. For the S.E.P. and PPGA packages: Valid delay timing for this signal is specified to 2.5 V +5%.
For the FC-PGA/FC-PGA2 packages: Valid delay timing for this signal is specified to 1.5 V +3%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
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Datasheet