243658-020 Datasheet, PDF (53/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
(for the FC-PGA/FC-PGA2 Packages)
T# Parameter
V1: BCLK VIL
V1: PICCLK VIL
V2: BCLK VIH
V2: PICCLK VIH
V3: VIN Absolute Voltage Range
V4: BCLK Rising Edge Ringback
V4: PICCLK Rising Edge Ringback
V5: BCLK Falling Edge Ringback
V5: PICCLK Falling Edge Ringback
Min
Nom Max
Unit Figure
Notes
0.50
V
11
0.70
V
11
2.00
V
11
2.00
V
11
–0.58
3.18
V
11
2.00
V
11
2
2.00
V
11
2
0.50
V
0.70
V
11
2
11
2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to FC-PGA/FC-PGA2 processors frequencies
and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
T3
V3
V4
V2
V1
V5
V3
T6
T4
T5
Datasheet
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