243658-020 Datasheet, PDF (47/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 27. System Bus AC Specifications (TAP Connection)^{1, 2, 3}
T# Parameter
T30: TCK Frequency
T31: TCK Period
T32: TCK High Time
T33: TCK Low Time
Min
Max
Unit
16.667
MHz
60.0
ns
25.0
ns
25.0
ns
T34: TCK Rise Time
5.0
ns
T35: TCK Fall Time
5.0
ns
T36: TRST# Pulse Width
40.0
ns
T37: TDI, TMS Setup Time
5.0
ns
T38: TDI, TMS Hold Time
14.0
ns
T39: TDO Valid Delay
1.0
10.0
ns
T40: TDO Float Delay
25.0
ns
T41: All Non-Test Outputs Valid Delay
2.0
25.0
ns
T42: All Non-Test Inputs Setup Time
25.0
ns
T43: All Non-Test Inputs Setup Time
5.0
ns
T44: All Non-Test Inputs Hold Time
13.0
ns
Figure
Notes
3
3
V_REF + 0.200 V, 10
3
V_REF – 0.200 V, 10
(V_REF – 0.200 V) –
3
(V_REF + 0.200 V),
4, 10
(V_REF + 0.200 V) –
3
(V_REF – 0.200 V),
4, 10
10
Asynchronous, 10
9
5
9
5
9
6, 7
9
6, 7, 10
9
6, 8, 9
9
6, 8, 9, 10
9
5, 8, 9
9
5, 8, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processors frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All
TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V (1.25 V for AGTL platforms).
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Datasheet
47