243658-020 Datasheet, PDF (5/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
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Clock Control State Machine...............................................................................16
BCLK to Core Logic Offset ..................................................................................48
BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49
System Bus Valid Delay Timings ........................................................................49
System Bus Setup and Hold Timings..................................................................49
System Bus Reset and Configuration Timings (For the S.E.P. and
PPGA Packages) ................................................................................................50
System Bus Reset and Configuration Timings (For the
FC-PGA/FC-PGA2 Package) ..............................................................................50
Power-On Reset and Configuration Timings.......................................................51
Test Timings (TAP Connection) ..........................................................................51
Test Reset Timings .............................................................................................51
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor
Edge Fingers .......................................................................................................54
Low to High AGTL+ Receiver Ringback Tolerance.............................................56
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................57
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA/FC-PGA2 Packages) ...........................................................................63
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ....................64
Processor Functional Die Layout (CPUID 0686h)...............................................67
Processor Functional Die Layout (up to CPUID 0683h)......................................67
Processor Substrate Dimensions (S.E.P. Package) ...........................................70
Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....70
Package Dimensions (PPGA Package) ..............................................................79
PPGA Package (Pin Side View)..........................................................................81
Package Dimensions (FC-PGA Package)...........................................................92
Package Dimensions (FC-PGA2 Package).........................................................94
Volumetric Keep-Out ...........................................................................................96
Component Keep-Out .........................................................................................96
Package Dimensions (FC-PGA/FC-PGA2 Packages) ........................................97
Top Side Processor Markings (PPGA Package)...............................................108
Top Side Processor Markings (FC-PGA Package) ...........................................108
Top Side Processor Markings (FC-PGA2 Package) .........................................108
Retention Mechanism for the Boxed Intel® Celeron^® Processor in the
S.E.P. Package .................................................................................................111
Side View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................111
Front View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................112
Boxed Intel^® Celeron^® Processor in the PPGA Package..................................113
Side View Space Requirements for the Boxed Processor in the PPGA
Package ............................................................................................................113
Conceptual Drawing of the Boxed Intel^® Celeron^® Processor in the
370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114
Dimensions of Mechanical Step Feature in Heatsink Base for the
FC-PGA/FC-PGA2 Packages ...........................................................................114
Top View Airspace Requirements for the Boxed Processor in the
S.E.P. Package .................................................................................................115
Datasheet
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