243658-020 Datasheet, PDF(49/128 Page) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

243658-020 Datasheet, PDF (49/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

◁

IntelÂ® CeleronÂ® Processor up to 1.10 GHz

Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform

CLK

0.7V (0.5V*)

1.7V (2.0V*)

1.25V

Tr = T5, T25, T34 (Rise Time)

Tf = T6, T26, T35 (Fall Time)

Th = T3, T23, T32 (High Time)

Tl = T4, T24, T33 (Low Time)

Tp = T1, T22, T31 (BLCK, TCK, PICCLK Period)

Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V.

For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V.

For the FC-PGA package, TCK is referenced to VREF Â±200mV.

Figure 4. System Bus Valid Delay Timings

CLK

Signal

Valid

Tpw

Tx = T7, T11, T29a, T29b (Valid Delay)

Tpw = T14, T14B, T15 (Pulse Width)

V = 1.0V for AGTL+ signal group;

For S.E.P and PPGA packages, 1.25V for CMOS, APIC and JTAG signal groups

For FC-PGA package, 0.75V for CMOS, APIC and TAP signal groups

Figure 5. System Bus Setup and Hold Timings

CLK

Signal

Ts Th

V Valid

Ts = T8, T12, T27 (Setup Time)

Th = T9, T13, T28 (Hold Time)

V = 1.0V for AGTL+ signal group;

For S.E.P. and PPGA packages, 1.25V for APIC and JTAG signal groups

For the FC-PGA package, 0.75V for APIC and TAP signal groups

Datasheet

▷