243658-020 Datasheet, PDF (36/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 10. System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages)
T# Parameter
Min Nom Max Unit Figure
Notes
System Bus Frequency
T1: BCLK Period
T2: BCLK Period Stability
T3: BCLK High Time
T4: BCLK Low Time
T5: BCLK Rise Time
• S.E.P.P. and PPGA
• FC-PGA/FC-PGA2
T6: BCLK Fall Time
• S.E.P.P. and PPGA
• FC-PGA/FC-PGA2
66.67
15.0
± 300
4.94
4.94
MHz
ns
ps
ns
ns
0.34
1.36
ns
0.40
1.6
ns
0.34
1.36
ns
0.40
1.6
ns
3 4, 5, 6
3 6, 8, 9
3
@>2.0 V ⁶
3
@<0.5 V ⁶
3
(0.5 V–2.0 V) ^{6, 10}
3 10, 11
3
(2.0 V–0.5 V) ^{6, 10}
3 10, 11
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core
pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization. Table 12 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to the Intel Celeron processor when operating at a system bus frequency of
66 MHz.
7. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications.
8. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
9. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer.
10.Not 100% tested. Specified by design characterization as a clock driver requirement.
11. BCLK Rise time is measure between 0.5V–2.0V. BCLK fall time is measured between 2.0 V–0.5 V.
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Datasheet