243658-020 Datasheet, PDF (126/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 7 of 7)
Signal
Type
Description
VCOREDET
(PGA packages
only)
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
VREF[7:0]
(PGA packages
only)
O ^TCheeleVroC_n^O®R_F^ED_C^E_-P^T _GsiAgn/FaCl ^{w-PilGl fAlo2atpfroorc2e.s0sVorcworitehparo1c.5eVsscoorsreavnodltwagilleb.e grounded for the}
The VID (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
O voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See Table 2 for
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+
inputs are differential receivers and will use this voltage to determine whether the
I _{signal is a logic high or logic low.}
For the FC-PGA/FC-PGA2 packages, VREF is typically 2/3 of VTT
7.1
Signal Summaries
Table 60 through Table 63 list attributes of the Celeron processor output, input, and I/O signals.
Table 60. Output Signals
Name
CPUPRES# (PGA
packages only)
FERR#
IERR#
PRDY#
SLOTOCC#
(S.E.P.P. only)
TDO
THERMDN
THERMTRIP#
VCOREDET
(PGA packages only)
VID[4:0] (S.E.P.P.)
VID[3:0] (PGA
packages)
Active Level
Low
Low
Low
Low
Low
High
N/A
Low
High
High
Clock
Asynch
Asynch
Asynch
BCLK
Asynch
TCK
Asynch
Asynch
Asynch
Asynch
Signal Group
Power/Other
CMOS Output
CMOS Output
AGTL+ Output
Power/Other
TAP Output
Power/Other
CMOS Output
Power/Other
Power/Other
126
Datasheet