243658-020 Datasheet, PDF (58/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
3.3.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. (See Figure 14 for an illustration of ringback.) Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table 34 for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor core, and Table 35 for guidelines on measuring ringback at the edge fingers. Table 36
lists the ringback specifications for the FC-PGA/FC-PGA2 packages.
Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Core (S.E.P. and PPGA Packages)
Input Signal Group
Non-AGTL+ Signals
Non-AGTL+ Signals
Transition
0→1
1→0
Maximum Ringback
(with Input Diodes Present) Unit
1.7
V
0.7
V
Figure
14
14
Notes
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement
(S.E.P. Package)
Input Signal Group
Non-AGTL+ Signals
Non-AGTL+ Signals
Transition
0→1
1→0
Maximum Ringback
(with Input Diodes Present) Unit
2.0
V
0.7
V
Figure
14
14
Notes
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Pins (FC-PGA/FC-PGA2 Packages)
Input Signal Group
Non-AGTL+ Signals
PWRGOOD
Non-AGTL+ Signals
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
0→1
0→1
1→0
VREF + 0.200
V
2.0
V
VREF – 0.200
V
Figure
16
16
16
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all FC-PGA/FC-PGA2 processor frequencies
and cache sizes.
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Datasheet