243658-020 Datasheet, PDF (44/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core
Pins (For S.E.P. and PGA Packages)
T# Parameter
Min
T21: PICCLK Frequency
2.0
T22: PICCLK Period
30.0
T23: PICCLK High Time
• S.E.P.P and PPGA
11.0
• FC-PGA/FC-PGA2
10.5
T24: PICCLK Low Time
• S.E.P.P and PPGA
11.0
• FC-PGA/FC-PGA2
10.5
T25: PICCLK Rise Time
0.25
T26: PICCLK Fall Time
0.25
T27: PICD[1:0] Setup Time
• S.E.P.P and PPGA
8.0
• FC-PGA/FC-PGA2
5.0
T28: PICD[1:0] Hold Time
2.5
T29: PICD[1:0] Valid Delay (S.E.P.P
and PPGA only)
1.5
T29a: PICD[1:0] Valid Delay (Rising
Edge) (FC-PGA/FC-PGA2
1.5
only)
T29b: PICD[1:0] Valid Delay (Falling
Edge) (FC-PGA/FC-PGA2
1.5
only)
Max
33.3
500.0
3.0
3.0
10.0
8.7
12.0
Unit
MHz
ns
Figure
3
Notes
ns
3
@>2.0 V
ns
3
@>1.7 V
ns
3
@<0.5 V
ns
3
@<0.7 V
ns
3
(0.5 V–2.0 V)
ns
3
(2.0 V–0.5 V)
ns
5
5
ns
5
5
ns
5
5
ns
4
5, 6, 7
ns
4
5, 6, 8
ns
4
5, 6, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V at the processor core pins.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
8. Valid delay timings for these signals are specified to 1.5 V +5%.
44
Datasheet