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243658-020 Datasheet, PDF (107/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz
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Intel® Celeron® Processor up to 1.10 GHz
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Q5
Q33
Q35
Q37
R2
R4
R6
R32
R34
R36
S1
S3
S5
S33
S35
S37
T2
T4
T6
T32
T34
T36
U1
U3
U5
U33
U35
U37
V2
V4
V6
V32
V34
V36
W1
W3
W5
W33
W35
Pin Name
GND
Reserved
Reserved
Reserved
Reserved
D17#
VREF3
VCCCORE
GND
VCCCORE
D8#
D5#
VCCCORE
Reserved
RTTCTRL
Reserved
VCCCORE
D1#
D6#
GND
VCCCORE
GND
D4#
D15#
GND
PLL2
Reserved
Reserved
GND
Reserved
VREF4
VCCCORE
GND
VCCCORE
D0#
Reserved
VCCCORE
PLL1
Reserved
Signal Group
Power/Other
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
AGTL+ I/O
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Reserved for future use
Power/Other
Reserved for future use
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Reserved for future use
Reserved for future use
Power/Other
Reserved for future use
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
Reserved for future use
Power/Other
Power/Other
Reserved for future use
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
W37
X4
X6
X20
X32
X34
X36
Y1
Y3
Y5
Y33
Y35
Y37
Z2
Z4
Z6
Z32
Z34
Z36
Pin Name
BCLK
RESET#7
Reserved
Reserved
GND
Reserved
GND
Reserved
A26#
GND
Reserved4
VCCCORE
GND
GND
A29#
A18#
VCCCORE
GND
Vcc2.5
Signal Group
System Bus Clock
Power/Other
Reserved for future use
Reserved for future use
Power/Other
Reserved for future use
Power/Other
Reserved for future use
AGTL+ I/O
Power/Other
Reserved for future use
Power/Other
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
NOTES:
1. VCC1.5 must be supplied by the same voltage
source supplying VTT on the motherboard.
2. Previously this pin functioned as the EDGCTRL
signal.
3. Previously, PGA370 designs defined this pin as a
GND. For flexible PGA370 designs, it must be left
unconnected (NC).
4. Previously, PGA370 designs defined this pin as a
GND.
5. Celeron processor in the FC-PGA/FC-PGA2
packages does not make use of this pin.
6. This pin is only reset for processors with a CPUID
of 0686h. For previous Celeron processors prior
to 0686h (not including 0686h) this pin is
reserved.
7. This pin is reserved for Celeron processors with a
CPUID of 0686h.
8. For CPUID of 0681h, this is a VSS. For other
068xh processors, this pin is a No Connect (NC).
Datasheet
107
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