243658-020 Datasheet, PDF (42/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Table 19. System Bus AC Specifications (CMOS Signal Group) ^{1, 2, 3, 4}
T# Parameter
Min
Max
Unit
Figure
T14: CMOS Input Pulse Width, except
PWRGOOD
2
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
4
BCLKs
4, 8
Notes
Active and
Inactive states
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK become stable.
Table 20. System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages)
T# Parameter
Min
Max
Unit Figure
Notes
T16: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Setup Time
4
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
2
BCLKs
20
BCLKs
6
Before deassertion
of RESET#
6
After clock that
deasserts RESET#
NOTES:
1. Unless
otherwise
noted,
all
specifications
in
this
table
apply
to
all
Intel ^®
Celeron^®
processor
frequencies.
Table 21. System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2
Packages)
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#)
4
Setup Time
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold
2
Time
T18: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
1
Setup Time
T19: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Delay Time
T20: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
2
Hold Time
BCLKs
20
BCLKs
ms
5
BCLKs
20
BCLKs
7
Before deassertion of
RESET#
7
After clock that
deasserts RESET#
7
Before deassertion of
RESET#, 3
7
After assertion of
RESET#, 2, 3
7
After clock that
deasserts RESET#, 3
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron FC-PGA/FC-PGA2 processors at all
frequencies and cache sizes.
2. For a reset, the clock ratio defined by these signals must be a safe value (their final or a lower-multiplier)
within this delay unless PWRGOOD is being driven inactive.
3. These parameters apply to processor engineering samples only. For production units, the processor core
frequency will be determined through the processor internal logic.
42
Datasheet