243658-020 Datasheet, PDF (51/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Figure 8. Power-On Reset and Configuration Timings
BCLK
Vcc_CORE, V_TT,
V_REF
PWRGOOD
V_{IL, max}
T_a
V_{IH, min}
T_b
RESET#
Configuration
(A20M#, IGNNE#,
INTR, NMI)
T_C
Valid Ratio
T_a = T15 (PWRGOOD Inactive Pulse)
T_b = T10 (RESET# Pulse Width)
T_c = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (FC-PGA)
Figure 9. Test Timings (TAP Connection)
TCK
TDI, TMS
Input
Signals
TDO
Output
Signals
1.25V
T_v
1.25V
T_r
T_x
T_y
T_r = T43 (All Non-Test Inputs Setup Time)
T_s = T44 (All Non-Test Inputs Hold Time)
T_u = T40 (TDO Float Delay)
T_v = T37 (TDI, TMS Setup Time)
T_w = T38 (TDI, TMS Hold Time)
T_x = T39 (TDO Valid Delay)
T_y = T41 (All Non-Test Outputs Valid Delay)
T_z = T42 (All Non-Test Outputs Float Delay)
Figure 10. Test Reset Timings
TRST#
1.25V
T_q
T_q = T37 (TRST# Pulse Width)
T_w
T_s
T_u
T_z
C
Datasheet
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