243658-020 Datasheet, PDF (22/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
open drain and should be pulled high to VCCCMOS. This ensures not only correct operation for
current Intel Celeron processors, but compatibility for future Intel Celeron processor products as
well.
The groups and the signals contained within each group are shown in Table 3. Refer to Section 7.0
for descriptions of these signals.
Table 3. Intel^® Celeron^® Processor System Bus Signal Groups
Group Name
AGTL+ Input
AGTL+ Output
AGTL+ I/O
CMOS Input⁴
CMOS Input
CMOS Output⁴
System Bus Clock
APIC Clock
APIC I/O⁴
TAP Input⁴
TAP Output⁴
Power/Other⁵
Signals
BPRI#, DEFER#, RESET#¹¹, RS[2:0]#, TRDY#
PRDY#
A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#⁸, D[63:0]#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#,
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#²,
STPCLK#
PWRGOOD^1,9
FERR#, IERR#, THERMTRIP#³
BCLK⁹
PICCLK⁹
PICD[1:0]
TCK, TDI, TMS, TRST#
TDO
CPUPRES#⁷, EDGCTRL⁷, EMI⁶, PLL[2:1]⁷, SLOTOCC#⁶, THERMDP, THERMDN,
VCC1.57, VCC2.57, VCCL25, VCC56, VCCCMOS7, VCCCORE, VCOREDET7, VID[3:0]⁷,
VID[4:0]⁶, VREF[7:0]⁷, VSS, VTT14, RTTCTRL¹², BSEL[1:0]¹⁰, SLEWCTRL¹³
NOTES:
1. See Section 7.0 for information on the PWRGOOD signal.
2. See Section 7.0 for information on the SLP# signal.
3. See Section 7.0 for information on the THERMTRIP# signal.
4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V
operation for the FC-PGA/FC-PGA2 packages.
5. VCCCORE is the power supply for the processor core.
VID[4:0] and VID[3:0] are described in Section 2.0.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
VCC5 is not connected to the Celeron processor. This supply is used for Voltage Transient Tools.
SLOTOCC# is described in Section 7.0.
BSEL is described in Section 2.7.2 and Section 7.0.
EMI pins are described in Section 7.0.
VCCL2 is a Pentium^® II processor reserved signal provided to maintain compatibility with the Pentium^® II
processor and may be left as a no-connect for “Intel Celeron processor-only” designs.
6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages.
8. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information.
9. These signals are specified for 2.5 V operation.
10.BSEL1 is not used in Celeron processors.
11. RESET# must always be terminated to VTT on the motherboard for PGA packages. On-die termination is not
provided for this signal on FC-PGA/FC-PGA2 packages.
12.For the FC-PGA/FC-PGA2 packages, this signal is used to control the value of the processor on-die
termination resistance. Refer to the specific platform design guide for the recommended pull-down resistor
value.
13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages.
14.S.E.P. Package and FC-PGA/FC-PGA2 packages.
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