243658-020 Datasheet, PDF (50/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages)
BCLK
RESET#
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T_u
T_t
T_v
T_w
T_x
Valid
T_t = T9 (AGTL+ Input Hold Time)
T_u = T8 (AGTL+ Input Setup Time)
T_v = T10 (RESET# Pulse Width)
T_w = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T_x = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package)
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T_u
T_t
T_v
T_y
T_z
T_x
Safe
Valid
T_w
Valid
T_t = T9 (AGTL+ Input Hold Time)
T_u = T8 (AGTL+ Input Setup Time)
T_v = T10 (RESET# Pulse Width)
T_w = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T_x = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
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