243658-020 Datasheet, PDF (43/128 Pages) Intel Corporation – Intel Celeron Processor up to 1.10 GHz

Intel^® Celeron^® Processor up to 1.10 GHz
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Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge
Fingers (for S.E.P. Package)
T# Parameter
T21’: PICCLK Frequency
T22’: PICCLK Period
T23’: PICCLK High Time
T24’: PICCLK Low Time
T25’: PICCLK Rise Time
T26’: PICCLK Fall Time
T27’: PICD[1:0] Setup Time
T28’: PICD[1:0] Hold Time
T29’: PICD[1:0] Valid Delay
Min
Max
Unit
Figure
Notes
2.0
33.3
MHz
30.0
500.0
ns
12.0
ns
12.0
ns
0.25
3.0
ns
0.25
3.0
ns
8.5
ns
3.0
ns
3.0
12.0
ns
3
3
3
3
3
5
5
5
5
4
5, 6, 7
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor
edge fingers. All APIC I/O signal timings are referenced at 1.25 V at the processor edge fingers.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
Datasheet
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