MB86967 Datasheet, PDF (96/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(8) Bus Timing (PC card mode, I/O write cycle)
(VDD = +5 V ± 5%, GND = 0 V, Ta = 0°C to +70°C)
Parameter
Value
Symbol
Unit
Min.
Max.
Setup time for address, CE1, CE2, REG prior to IOWR assert
t1
Hold time for address, CE1, CE2 after IOWR negate
t2
Hold time for REG after IOWR negate
t3
Setup time for write data input
t4
Hold time for write data input
t5
Write pulse width
t6
Output delay time for IOIS16 assert from address
t7
Output delay time for IOIS16 negate from address
t8
5
—
ns
5
—
ns
0
—
ns
10
—
ns
5
—
ns
36
—
ns
—
35
ns
—
35
ns
Output delay time for WAIT assert from IOWR assert
t9
5*¹
35*¹
ns
Output delay time for WAIT negate from IOWR assert
t10
—
175*²
ns
*1: WAIT is asserted only when the write access conflicts with that of the network on writing the buffer memory
port (BMPR8).
*2: WAIT is asserted only when the write access conflicts with that of the network on writing the buffer memory
port (BMPR8).
This value will be 2.15 µs when the bus write error occurs on writing the buffer memory port.
PA
REG
CE1, CE2
IOWR
IOIS16
WAIT
PD
t1
t7
t6
t9
t10
t4
t2
t3
t8
t5
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