MB86967 Datasheet, PDF (95/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(7) Bus Timing (PC card mode, I/O read cycle)
(VDD = +5 V ± 5%, GND = 0 V, Ta = 0°C to +70°C)
Parameter
Value
Symbol
Unit
Min.
Max.
Setup time for address, CE1, CE2, REG prior to IORD assert
t1
Hold time for address, CE1, CE2 after IORD negate
t2
Hold time for REG after IORD negate
t3
Output delay for read data after IORD assert
t4
Output hold for read data after IORD negate
t5
Read pulse width
t6
Output delay for INPACK assert after IORD assert
t7
Output delay for INPACK negate after IORD negate
t8
5
—
ns
5
—
ns
0
—
ns
—
44
ns
10
—
ns
30
—
ns
—
45
ns
—
45
ns
Output delay time of WAIT assert from IORD assert
t9
5*¹
35*¹
ns
Output delay time of WAIT negate from IORD assert
t10
—
175*²
ns
*1: WAIT is asserted only when the write access conflicts with that of the network on reading the buffer memory
port (BMPR8).
*2: WAIT is asserted only when the write access conflicts with that of the network on reading the buffer memory
port (BMPR8).
This value will be 2.15 µs when the bus write error occurs on reading the buffer memory port.
PA
REG
CE1, CE2
IORD
INPACK
WAIT
PD
t6
t1
t7
t9
t10
t4
t2
t3
t8
t5
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