MB86967 Datasheet, PDF (52/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(5) BMPR13: DMA Burst/Transceiver Mode Control Register
The BMPR13 sets the DMA transfer cycle count between the host system and MB86967 and the operation
modes of the 10BASE-T transceiver.
Read
Write
Initial Value
Bit 7
I/O BASE
UNLOCK
1
Bit 6
0
0
Bit 5
LINK
TEST
ENA
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
DMA
BRST 1
0
Bit 0
DMA
BRST 0
0
Bit no. Bit name
7 I/O BASE
UNLOCK
6 Not used
5 LINK TEST
ENA
4 to 2 Not used
1 and 0 DMA BRST
1 and 0
Operation
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Value
0
1
—
0
1
—
—
Function
The I/O base address is not changed even after an I/O-read
operation to address X12H.
An I/O-read operation to address X12H increments the values
of the I/O base address select signals (IOSEL0 to IOSEL2),
causing a change in the I/O base address (This is valid only in
the jumperless ISA bus mode).
The read value of this bit is always 0.
Writing 1 is prohibited. Always write 0 to this bit at writing.
The link test on the 10BASE-T transceiver is enabled.
The link test on the 10BASE-T transceiver is disabled.
The read values of these bits is always 0.
Writing 1 is prohibited. Always write 0 to these bits at writing.
The DMA transfer cycle count is set by one bus request
(These bits are invalid in the PC card mode).
BRST1 BRST0 DAM Transfer Cycle Count (Max.)
0
0
1 (single DMA)
0
1
4
1
0
18
1
1
12
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