MB86967 Datasheet, PDF (10/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
• System interface pins in general-purpose mode
Pin no. Symbol
Pin name
I/O
Function
18 to 23,
25,
27 to 29,
85,
87 to 91
SD0 to SD15
SYSTEM DATA BUS
BD These pins are used as a data bus for data exchange
between the host system and the MB86967. They
are also used for DMA transfer. In the 8-bit bus mode
(bit 5 of DLCR6 = 1), only the 8 lower bits (SD0 to
SD7) are used.
4 to 7
SA0 to SA3
SYSTEM ADDRESS
BUS
ID These pins are used for input of system address
signals for selecting MB86967 registers, BOOT
PROM, and ID PROM.
82
ECS
ENABLE CHIP
SELECT
IU This pin is used for input of Active-Low chip select
signals.
64
HWRST
CHIP RESET
ISU This pin is used for input of hardware reset signals
(Active High).
15
IOR
I/O READ
IU This pin is used for input of I/O read strobe signals
(Active Low).
17
IOW
I/O WRITE
IU This pin is used for input of I/O write strobe signals
(Active Low).
13
EOP
END OF PROCESS ID This pin is used for input of signals indicating the end
of DMA transfer between the buffer memory and host
system. At EOP input, the next DREQ is not output
and the handshaking cycle is terminated. Either
Active High or Active Low can be selected.
12
DMACK
DMA
ID This pin is used for input of Active-Low signals and
ACKNOWLEDGE
for connection of DMAC acknowledge signals
indicating that the DMAC is read for transmitting and
receiving data to and from buffer memory.
11
BHE
SYSTEM BUS HIGH ID This pin is used for input of Active-Low signals and
ENABLE
for controlling byte/word transfer. In the 16-bit data
bus mode (bit 5 (SB/SW)of DLCR6 = 0), this pin,
together with SA0, controls word transfer and the
transfer of upper and lower bytes on the data bus.
SB/SW
0
0
0
0
1
SBHE
0
0
1
1
×
SA0
Function
0 Word transfer
1
Transfer of upper bytes on
data bus (SD15 to SD8)
0
Transfer of lower bytes on
data bus (SD7 to SD0)
1 Unused
×
Byte transfer
(SD7 to SD0)
×: don’t care
92
INT
INTERRUPT
REQUEST
O This pin is used for output of Active-Low interrupt
request signals.
2
DREQ
DMA REQUEST
O This pin is used for input of DMA transfer request
(Active High)
signals.
(Continued)
10