MB86967 Datasheet, PDF (33/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
10.2 Transmitter Circuits
The transceiver’s transmitter section receives the encoded data from the Manchester encoder and the twisted-
pair network via the TPO circuit. Advanced integrated pulse-shaping produces an output signal that is
predistorted and prefiltered to meet the 10BASE-T jitter template on the TPON and TPOP pins.
During idle periods, the MB86967 transmits link integrity test pulses on the TPO circuit if LINK TEST EN,
BMPR13<5>, is asserted.
10.3 Jabber Control
An on-chip watchdog timer prevents the chip from locking into a continuous transmit mode. When a transmission
exceeds the maximum time limit (specified for the MB86967 as 20 to 150 msec), the watchdog timer disables
the transmit and loopback functions and asserts the JABBER error status bit, DLCR0<3>, generating an interrupt
if so enabled. Before the MB86967 can exit the jabber state, the transmit data circuit must remain idle for between
0.25 and 0.75 seconds.
10.4 SQE Test
The transceiver supports the signal quality error (SQE) test function specified in the standard. After every
successful transmission on the 10BASE-T network, the MB86967 transceiver section transmits the SQE signal
to the controller for 10±5 bit times over the internal CI circuit. BMPR15<1> reflects the status of this SQE test.
10.5 Receive Input Circuits
Valid received signals from the twisted-pair network connection (the TPI circuit) pass through on-chip filters to
the data decoder.
An internal intelligent squelch function discriminates noise from link test pulses and valid data streams. The
receiver is activated only by valid data streams above the squelch level and with proper timing. If the differential
signal at the TPI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical),
the receiver enters the idle state.
10.6 Data Decoder
The data decoder section performs three functions on the received data: clock recovery, carrier detection, and
Manchester data decoding. Carrier detection is indicated to the receiver section by assertion of the internal
carrier sense signal, which occurs shortly after the received data signals appear. Carrier sense status can be
monitored via DLCR0<6>. Clock recovery and data separation are accomplished by an internal phase-locked
loop. The recovered clock is supplied to the receiver together with the recovered NRZ serial data stream.
10.7 Reverse Polarity
The transceiver polarity reverse circuit uses link pulses and end-of-frame data to determine the polarity of the
received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected
without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are
received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the
transceiver enters the link fail state and no valid data or link pulses are received within 96 to 128 milliseconds,
polarity resets to the default uninverted condition. If Link Integrity testing is disabled, polarity detection is based
only on received data.
The transceiver automatically corrects reversed polarity. Polarity reversal is reported via BMPR15<3>.
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