MB86967 Datasheet, PDF (41/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(4) DLCR3: Receive Interrupt Enable Register
The DLCR3 register enables a receive interrupt. When the bit corresponding to the status bit of DLCR1 is set
to 1, the external interrupt INT is asserted when the status bit is set.
Read/Write
Initial Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENA PKT ENA BUS ENA DMA ENA ENA RX ENA ALG ENA
ENA
RDY RD ERR EOP RMT RST SRT PKT ERR CRC ERR OVRFLO
0
0
0
0
0
0
0
0
Bit no. Bit name Operation
7 ENA PKT RDY Read/Write
6 ENA BUS RD Read/Write
ERR
5 ENA DMA EOP Read/Write
4 ENA RMT RST Read/Write
3 ENA RX SRT Read/Write
ERR
2 ENA ALG ERR Read/Write
1 ENA CRC ERR Read/Write
0 ENA OVRFLO Read/Write
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Disables PKT RDY interrupt
Enables TMT OK interrupt
Disables BUS RD ERR interrupt
Enables BUS RD ERR interrupt
Disables DMA EOP interrupt
Enables DMA EOP interrupt
* : This bit is invalid in the
PC card mode.
Disables RMT RST interrupt
Enables RMT RST interrupt
Disables RX SRT ERR interrupt
Enables RX SRT ERR interrupt
Disables ALG ERR interrupt
Enables ALG ERR interrupt
Disables CRC ERR interrupt
Enables CRC ERR interrupt
Disables OVRFLO interrupt
Enables OVRFLO interrupt
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