MB86967 Datasheet, PDF (8/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
• System interface pins in ISA bus mode
Pin no. Symbol
Pin name
18 to 23,
25,
27 to 29,
85,
87 to 91
SD0 to SD15
SYSTEM DATA BUS
4 to 13 SA0 to SA9 SYSTEM ADDRESS
BUS
64
CHRESET
CHIP RESET
(Active High)
15
IOR
I/O READ
(Active Low)
17
IOW
I/O WRITE
(Active Low)
63
AEN
ADDRESS ENABLE
(Active High)
65
EOP
END OF PROCESS
(Active High or Active
Low)
14
ALE
ADDRESS LATCH
ENABLE
82
SBHE
SYSTEM BUS HIGH
ENABLE
I/O
Function
BD These pins are used as data buses for data
exchange between the host system and the
MB86967. They are also used for DMA transfer. In
the 8-bit bus mode (bit 5 of DLCR6 = 1), only the 8
lower bits (SD0 to SD7) are used.
ID These pins are used for input of system address
signals for selecting LAN controller registers.
ISU This pin is used for input of hardware reset signals.
IU This pin is used for input of I/O read strobe signals.
IU This pin is used for input of I/O write strobe signals.
ISD This pin is used for input of signals indicating that the
DMA controller controls the system bus.
ID This pin is used for input of signals indicating the end
of DMA transfer between the buffer memory and host
system. At input of EOP, the next BREQ is not output
and the handshaking cycle is terminated.
ID This pin is used for input of signals indicating that the
addresses of SA0 to SA9 are determined.
IU This pin is used for controlling byte/word transfer. In
the 16-bit data bus mode (bit 5 (SB/SW) of DLCR6 =
0), this pin, together with SA0, controls word transfer
and the transfer of upper and lower bytes on the data
bus.
SB/SW
0
0
0
0
1
SBHE
0
0
1
1
×
SA0
Function
0 Word transfer
1
Transfer of upper bytes on
data bus (SD15 to SD8)
0
Transfer of lower bytes on
data bus (SD7 to SD0)
1 Unused
×
Byte transfer
(SD7 to SD0)
×: don’t care
2
DREQ
DMA REQUEST
O This pin is used for output of DMA transfer request
(Active High)
signals.
(Continued)
8