MB86967 Datasheet, PDF (27/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
7.6 Skip Packet
Writing a ‘1’ to BMPR14<2> commands the buffer controller to skip the balance of the current receive packet in
memory. The bit can then be read to determine completion of the skip process is complete (within 300 ns). If
there is another packet, the bit returns to 0 when the chip is ready to read the next packet.
DATA
STATUS
RESERVED
LENGTH LSB
LENGTH MSB
DATA
STATUS
RESERVED
LENGTH LSB
LENGTH MSB
DATA
PACKET N
PACKET N + 1
UNUSED BUFFER AREA
STATUS
RESERVED
LENGTH LSB
LENGTH MSB
DATA
Figure 6 Receive Buffer Detail
7.7 Receive Packet Header
The receive packet header contains four bytes and is stored in the receive buffer preceding each packet. The
receive packet header comprises one byte of packet status, an unused byte and two bytes (11 bits) for packet
length. Bits 1 through 4 of the status byte are an image of the same bits in the Receive Status Register, DLCR1,
with respect to the packet that follows. Bit 5 is the GOOD PKT bit, which when set to 1 indicates that no errors
were detected in the packet. Bits 0, 6 and 7 are unused and are always set to 0. See Table 2.
The length stored in bytes 3 and 4 of the header specifies the length of the portion of the packet stored in the
buffer. This length specification is in bytes, regardless of whether the system interface is programmed for byte
or word mode. During reception, the MB86967 strips the Preamble field and checks and strips the CRC field,
so, as is the case for the transmit buffer, those fields of the packet are not stored in the buffer. The length
specification thus includes only the Destination ID, Source ID, Length, and Data fields of the incoming packet.
27