MB86967 Datasheet, PDF (53/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(6) BMPR14: Receiver Control/Transceiver Interrupt Enable/Shutdown Register
BMPR14 controls interrupts from the receiver buffer pointer and 10BASE-T transceiver.
Read
Write
Initial Value
Bit 7
0
0
Bit 6
ENA LKF
INT
0
Bit 5
0
0
Bit 4
SHUT
DWN
MODE
0
Bit 3
TST3
0
0
Bit 2
Bit 1
SKIP RX ENA
PKT SQE INT
0
0
Bit 0
ENA
FILTER
0
Bit no. Bit name
7 Not used
Operation
Read/Write
6 ENA LKF INT Read/Write
5 Not used
4 SHUT DWN
MODE
Read/Write
Read/Write
3 TST3 (Chip Test Read/Write
3)
2 SKIP RX PKT Read/Write
1 ENA SQE INT Read/Write
0 FILTER SELF Read/Write
RX
Value
—
0
1
—
0
1
—
0
1
0
1
0
1
0
1
Function
The read value of this bit is always 0.
Always write 0 to this bit at writing.
The link fail interrupt is disabled.
The link fail interrupt is enabled.
The read value of this bit is always 0.
Always write 0 to this bit at writing.
When bit 5 (STBY) of DLCR7 is set, the MB86967 enters the
standby state (oscillation continues).
When bit 5 (STBY) of DLCR7 is set, the MB86967 enters the
shutdown state (oscillation stops).
This a chip test bit. Always write 0 to this bit at writing to the
BMPR14. Writing 1 to this bit during normal operation is
prohibited.
Skipping the receiver buffer pointer is completed.
The receiver buffer pointer is being skipped (updated),
indicating the transient state from when 1 is written to this bit
until skipping the pointer is completed (about 200 ns).
Not affected.
The receiver buffer pointer is not skipped.
When 1 is written to this bit, the receiver buffer pointer is
skipped up to the beginning of the next packet. This bit is
cleared automatically when skipping is completed.
If the packet to be skipped is the last one in the receiver buffer,
the BUF EMP bit of DLCR5 is set after the receiver buffer
pointer is skipped.
This function works only after reading the receive packet
header (4 bytes). And, it is prohibited to write “1” when the
remainder of the packet becomes 8-byte.
The signal quality error interrupt is disabled.
The signal quality error interrupt is enabled.
When the Address Match Mode bits AM1 and AM0 are 11, the
packet transmitted from the self office is also received.
When the Address Match Mode bits AM1 and AM0 are 11, the
packet transmitted from the self office is not received.
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