MB86967 Datasheet, PDF (18/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
s FUNCTIONAL DESCRIPTION
1. Local Buffer Configurations
The MB86967 is designed to operate with local buffer which holds packets received from the host processor
prior to transmission and assembles packets received from the network before they are delivered to the host
processor. The buffer is implemented by using a single byte-wide SRAM whose size is selected via DLCR6<1>
as 8 kbytes (DLCR6<1> = 0) or 32 kbytes DLCR6<1> = 1).
See Buffer Access section for information on how the host accesses the buffer memory.
2. Crystal Oscillator
The clock rate of 10 Mbits/s specified by the international LAN standard, ISO/ANSI/IEEE 8802-3, is derived from
an on-chip oscillator that is controlled by a 20 MHz crystal connected across pins 61 and 62 (CLKO and CLKI).
Capacitance specified by the crystal manufacturer must be connected as shown in Figure 1 to stabilize the
effects of stray capacitance that may vary crystal frequency. The 20 MHz clock also serves as an internal phase-
locked loop (PLL) reference for decoder clock recovery.
Use a crystal with the following specifications: quartz (AT-cut); 20-MHz; frequency acurracy of ±50ppm at 25°C
and ±100ppm at 0°C to 70°C; parallel resonant with 20 pF-load in fundamental mode.
MB86967
CLKO
CLKI
20 MHz
20 pF
20 pF
Figure 1 Crystal Oscillator Connection
3. Byte-Order Control
Byte-order control provided by BYTESWEAP bit, DLCR7<0>, provides compatibility with various higher-level
protocols, such as TCP/IP and XNS. These protocols may have a different order for transmission of the bytes
within a word. When BYTESWEAP is low, the least-significant byte of the word transmits first, followed by the
most-significant. When BYTESWEAP is set high, the byte order reverses. This feature applies only when the
system bus operates in 16-bit (word) mode.
The byte-order control works by reversing, or not reversing, the bytes of all words as they pass between the
buffer memory and the system bus. Thus all data stored in the transmit buffer or retrieved from the receive buffer
is affected, including nontransmitted headers. This control bit does not affect the MB86967 registers other than
the Buffer Memory Port registers, BMPR8 and BMPR9. When using this feature, ensure the reversal of header
information as well as packet data in the software driver code. See Table 1 for examples of using least..most
and most..least byte ordering.
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