MB86967 Datasheet, PDF (20/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
5. Buffer Access
The Buffer Memory Port register pair BMPR8 and BMPR9 provide 8- or 16-bit data access to the receive and
transmit buffers through on-chip FIFOs. To eliminate the need for complicated directional control, FIFOs are
dedicated to each direction of data transfer. Writing to the transmit buffer can be interleaved with reading from
the receive buffer, with the MB86967 automatically maintaining buffer memory pointers, thus relieving the host
of that task. The Buffer Memory port register pair is at address 08H when DLCR7<3:2> are programmed to ‘10’
to select the Buffer Memory Port register set. When using DMA, the buffer memory port is automatically selected
when the DMA Acknowledge input, DMACK, is asserted. The host accesses are byte-wide when the system is
configured for byte-wide operation and word-wide when the system interface is configured for word-wide
operation. In the latter mode, byte-wide access to the buffer memory port is not supported.
Data can transfer from the host memory to the transmit buffer, or from the receive buffer to host memory by
using string moves, single-transfer programmed I/O moves, or DMA. Select the method that yields the highest
system-level efficiency. A rapid transfer process results in best performance. Slow transfer can result in poor
throughput and performance, and cause the receive buffer to overflow and lose packets.
6. DMA Operation (ISA, Generic Mode Only)
The MB86967 supports single-cycle and burst DMA operation for data transfers between the host and the packet
buffer. Hand-shaking between the MB86967 and the external DMA controller is accomplished by the DREQ and
DMACK signals. The end of process input, when asserted by the system DMA controller during a transfer cycle,
terminates DMA activity after completion of the current cycle. If a DMA interrupt (DLCR3<5>) is enabled, the
MB86967 generates an interrupt after completion of DMA activity.
Usually only one DMA operation will be run at a time, although the MB86967 could run two interleaving
operations, one reading and one writing. There is only one DMA EOP bit, and only one DREQ pin and one
DMACK pin, so most hosts could not support more than one DMA operation at a time.
6.1 DMA Write (Transmit) ISA, Generic Mode Only
Setting the TX DMA Enable bit, BMPR12<0>, enables DMA transfer of data packets from the host memory to
the MB86967 transmit buffer. The DMA burst control bits, BMPR13<1:0>, set the maximum number of data
transfer cycles (bytes or words) in a single bus acquisition to be 1, 4, 8, or 12. The MB86967, when ready to
accept data from the host, sets the DMA request output, DREQ, and the host responds by asserting DMA
acknowledge, DMACK, followed by Write Strobe, WR, and placing data on the data bus. The MB86967 asserts
the RDY(RDY) output when ready to complete the current data-transfer cycle. (The assertive states of the
RDY(RDY) output and the EOP(EOP) input are independently programmable.) The MB86967 accepts the data
byte/word into its bus write FIFO and later moves it into buffer memory. At the close of a transfer cycle, the host
negates WR. In burst mode and depending on the value of the DREQ EXTND bit, DLCR4<2>, the MB86967
negates DREQ at the next-to-last or last transfer cycle of the burst. The host DMA then completes the last one
or two transfer cycles and negates DACK to terminate the burst. To start another burst, the MB86967 reasserts
DREQ.
The DMA controller asserts the end of process input, EOP(EOP), concurrent with the last required data-transfer
cycle to indicate completion of the entire transfer process. This action sets the DMA EOP status bit, DLCR1<5>,
and discontinues further data requests from the MB86967. The MB86967 will also generate an interrupt if the
DMA EOP interrupt enable bit, DLCR3<5>, is high. The host can use this interrupt to begin action to close the
process. The host should reset the MB86967 DMA logic and clear the interrupt by writing 00H to BMPR12.
Note: DMA EOP, DLCR1<5> must be cleared to close the transmit DMA process before attempting another
DMA process. This is accomplished by writing 00H to BMPR12. When this is done, the DMA EOP bit will
clear automatically, clearing the EOP status and interrupt, (if enabled) so it is not necessary to clear the
interrupt separately.
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