MB86967 Datasheet, PDF (51/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(4) BMPR12: DAM Enable Register
The BMPR12 controls DMA transfer between the host system and the MB86967.
Read
Write
Initial
Value
Bit 7
×
0
×
Bit 6
×
0
×
Bit 5
×
0
×
Bit 4
×
0
×
Bit 3
LONGPKT
RCV DIS
0
Bit 2
0
0
Bit 1
DMA
RENA
0
Bit 0
DMA
TENA
0
Bit no. Bit name Operation
7 to 4 Not used
Read
Write
3 LONGPKT RCV Read/Write
DIS
2 Not used
1 DMA RENA
Read/Write
Read/Write
0 DMA TENA
Read/Write
Value
—
0
0
1
—
0 (*1)
1 (*2)
0 (*1)
1 (*2)
Function
The read values of these bits are always undefined.
Writing 1 is prohibited. Always write 0 at writing.
The receive long packet removal function is enabled.
Packets with a length of 1792 bytes or more are not received.
The receive long packet removal function is disabled.
Packets with a length of up to 2047 bytes cannot be received
normally.
The read value of this bit is always 0.
Writing 1 is prohibited. Always write 0 at writing.
DMA read operation is disabled.
DMA read operation (reading from
receiver buffer) is enabled.
The DMA write operation is
disabled.
* : Writing 1 to this bit is
prohibited in the PC
card mode. Always
write 0 to this bit.
The DMA write operation (writing to
receiver buffer) is enabled.
*1: The DLCR1 DMAEOP bit is cleared if the DMA RENA bit and DMA TENA bit are set to “00”.
*2: Writing “11” to both DMA RENA bit and DMA TENA bit is prohibited.
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