MB86967 Datasheet, PDF (26/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
buffer memory, FIFO size and depth are unimportant in this architecture, and need not be considered in system
timing considerations.
A status bit in one of the MB86967’s internal registers informs the host when one or more packets are resident
in the receive buffer and available to be read. The host retrieves these packets from the buffer memory by
successive reads of BMPR8. Once a data byte/word is read from the buffer memory, internal pointers are
advanced to the next byte/word. As data is thus read by the system, that memory becomes available for reception
of new packets. The MB86967 automatically rejects an incoming packet if there is not enough buffer space to
fully receive that packet. Therefore, there is no chance for packets already received to be ‘overrun’ by incoming
packets.
LENGTH LSB
LENGTH MSB
DATA 1
LENGTH LSB
LENGTH MSB
DATA 2
LENGTH LSB
LENGTH MSB
DATA 3
LENGTH LSB
LENGTH MSB
DATA 4
PACKET 1
PACKET 2
DATA n
UNUSED BUFFER AREA
Figure 5 Transmit Buffer Detail
When DLCR5<5>, the ACPT BAD PKTS bit, is set to a ‘0’ (disabled), detection of a bad incoming packet causes
the MB86967 to release the buffer space in which that packet is contained and to reset its internal pointers so
as to use that space for the next incoming packet. If this bit is set to a ‘1’, a packet with a CRC or alignment error
will be accepted and the appropriate error bits in the status field of its header will be set. The same applies to
DLCR5<3>, ACPT SHORT PKTS, which when high allows retention of packets below 60 bytes in length,
excluding Preamble and CRC (which is shorter than IEEE 802.3 minimum packet size).
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