MB86967 Datasheet, PDF (21/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
After finishing the loading of packets into the buffer, the host initiates packet transmission. This is done by loading
the number of packets to be transmitted into the Transmit Start Register, BMPR10<6:0>, and asserting the
Transmit Start bit, TXST, of the same register, BMPR10<7>.
6.2 DMA Read (Receive) ISA, Generic Mode Only
The MB86967 indicates that it has received packets and stored them in the packet buffer with status bits or
interrupts. Before attempting to transfer a packet from the buffer, the host processor should read the RX BUF
EMPTY bit, DLCR5<6>. If this bit is 0, there are one or more packets ready for transfer in the receive buffer.
After reading each packet, the host will check this bit again to see if there are more.
Prior to beginning the transfer of a packet from the receive buffer to host memory via DMA, the host must first
read the four-byte receive packet header from the buffer to obtain the packet status and the length of the packet
in bytes. Calculating from the packet length the number of DMA cycles needed to read the packet, the host will
load that number into the cycle counter of the host DMA controller. Next, RX DMA EN, BMPR12<1>, is set to
high to enable DMA read operation to transfer the packet to host memory. The DMA burst control bits,
BMPR13<1:0>, set the maximum number of data transfer cycles (bytes or words) in a single bus acquisition to
be 1, 4, 8, or 12. When it is ready to begin, the MB86967 asserts its DMA Request output, DREQ. The host
responds by asserting DMA Acknowledge, DMACK, followed by the Read Strobe, RD. The MB86967 will assert
its RDY(RDY) output when it has placed the byte/word on the data bus and is ready to complete the data transfer
cycle. The system memory will accept the data, then the host negates RD. The MB86967 shifts the data down
in its bus read FIFO, then moves its internal read pointer to point to the next byte/word in the buffer, moving it
into the FIFO.
In burst mode and depending on the value of the DREQ EXTND bit, DLCR4<2>, the MB86967 negates DREQ
at the next-to-last or last transfer cycle of the burst. The host DMA then completes the last one or two transfer
cycles and negates DMACK to terminate the burst. The MB86967 reasserts DREQ to repeat the process if it
can transfer more data after the host negates DMACK. The DMA controller asserts the end of process input,
EOP(EOP) concurrent with the last byte/word data transfer to indicate completion of the entire process. The
MB86967 then stops requesting more DMA cycles.
When EOP(EOP) is asserted by the host DMA controller, the DMA EOP bit, DLCR1<5>, will be set high, and
an interrupt will also be generated, provided it is enabled by a high in the associated interrupt enable bit,
DLCR3<5>. This interrupt can be used by the host to initiate the final actions to close the DMA process. The
interrupt is cleared and the DMA is disabled and reset by writing 00H to the DMA Enable Register, BMPR12.
Note: Clearing RX DMA EN must be done to close the receive DMA process before attempting another DMA
process. This is accomplished by writing 00H to BMPR12. When this is done, the DMA EOP bit will clear
automatically, clearing the EOP status and interrupt, so it is not necessary to clear the interrupt separately.
After completion of the DMA process, RX DMA EN must be reasserted when the host wants to begin reading
another packet from the receive buffer by using DMA.
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