MB86967 Datasheet, PDF (45/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(7) DLCR6: Control Register 1
DLCR6 sets the MB86966 operation modes.
Read/Write
Initial Value
Bit 7
ENA DLC
1
Bit 6
100NS/
150NS
0
Bit 5
SB/SW
1
Bit 4
BB/BW
1
Bit 3
TX BUF
SIZE 1
0
Bit 2
TX BUF
SIZE 0
1
Bit 1
BUF
SIZE 1
1
Bit 0
BUF
SIZE 0
0
Bit no. Bit name Operation
7 ENA DLC
Read/Write
(Enable Data
Link Controller)
6 100NS/150NS Read/Write
(SRAM Cycle
Time Select)
5 SB/SW
Read/Write
(System Bus
Width Select)
4 BB/BW
Read
(Buffer Memory
Bus Width)
Write
3 and 2 TX BUF SIZE 1 Read/Write
TX BUF SIZE 0
(Transmitter
Buffer Size)
Value
0
1
0
1
—
1
—
—
Function
When 0 is written to this bit, the MB86967 is ready for
transmitting and receiving. When this bit is 0, the node ID
register and multicast address register cannot be accessed.
The data link controller and buffer manager in the MB86967
are initialized and both the transmitter and receiver buffers are
also initialized.
Sets cycle time of external SRAM to 150 ns
Sets cycle time of external SRAM to 100 ns.
In this case, use SRAM with an access time of 80 ns or less.
Selects width of system data bus
SB/SW
System Data Bus
0
16 bit
1
8 bit
• PC Card Mode
When 1 is written to bit 5 (IOIS8) of the CCR1, the SB/-SW
bit is set to 1, placing the system data bus in the byte
transfer mode. When 0 is written, the SB/-SW bit is set to 0,
placing the system data bus in the word transfer mode.
In the PC card mode, writing to the SB/-SW bit is performed
by CCR1. Writing from DLCR6 does not affect bit 5.
• General-purpose Bus Mode
The reversed value of the SB/SW bit is output to the
external pin SB/SW.
The width of the buffer memory data bus is fixed to 8 bits. The
read value of this bit is always 1.
Not affected
Sets size of transmitter buffer.
TX BUF SIZE _Bank
Bank Buffer
1
0 ^{Capacity Count Capacity}
0
0
2 Kbyte
1
2 Kbyte
0
1
2 Kbyte
2
4 Kbyte
1
0
4 Kbyte
2
8 Kbyte
1
1
8 Kbyte
2
16 Kbyte
* : This register is accessible only for the device initialization.
(Continued)
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