MB86967 Datasheet, PDF (105/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(16)Single DMA Access Timing
Parameter
Delay time for DREQ negate output (from DMACK
assert)
Delay time for DREQ assert output (from DMACK
negate)
EOP pulse width
Delay time for EOP assert input
Setup time for EOP negate
Setup time for DMACK
Hold time for DMACK input
(VDD = +5 V ± 5%, GND = 0 V, Ta = 0°C to +70°C)
Value
Symbol
Unit
Min.
Typ.
Max.
t1
—
—
21
ns
t2
—
—
19
ns
t3
10
—
—
ns
t4
3
—
—
ns
t5
3
—
—
ns
t6
0
—
—
ns
t7
3
—
—
ns
DREQ
t1
t2
DMACK
t6
IOR, IOW
EOP^*
EOP^*
t4
t3
t7
t5
* : EOP input allows the values of EOP/EOP register values for bit 1 of DLCR7 to toggle between EOP (active high) and
EOP (active low).
Note: IOCHRDY signal timing is identical as that of bus timing.
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