MB86967 Datasheet, PDF (24/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
At reset, internal pointers are initialized to point to the beginning of one of the transmit buffers. Each time the
host writes data to the buffer via the Buffer Memory Port Register, an internal pointer is advanced to the next
memory location within the transmit buffer. Once a data byte/word is written, it cannot be read and the internal
pointer cannot be reversed.
When the host completes loading the transmit buffer, it writes the number of packets it has loaded into TX PKT
CNT, BMPR10<6:0> and sets the transmit start bit, BMPR10<7>. When this occurs, the MB86967 will switch
banks and will start transmitting at the earliest opportunity. Another automatically-managed pointer, the transmit
read pointer, sequences through the bank being transmitted to read the packet data into the transmitter through
its FIFO. If a collision occurs, the packet will be automatically retransmitted after a pseudo-random waiting
interval called the backoff interval. If there are multiple packets in the buffer, the MB86967 will continue down
the list until all are transmitted. Upon reaching the end of the list or chain of packets, the transmitter will stop,
update its status bits and, if enabled, generate an interrupt. The details of this operation are described in the
section on packet transmission.
7.4 Transmit Packet Header
As shown in Figure 5, each packet within one transmit bank is separated by a non-transmitted, two-byte header
containing an 11-bit value which specifies the length of the associated packet in bytes. The length specification
includes only what is stored in the buffer (shown in the figure as ‘DATA’), which are the Destination ID, Source
ID, Length, and Data fields of the packet. It does not include the Preamble and CRC fields which are generated
by the MB86967 as it transmits the packet, and therefore are not stored in the buffer.
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