MB86967 Datasheet, PDF (38/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(2) DLCR1: Receive Status Register
DLCR1 indicates the receive status of the data link controller. The external interrupt INT is asserted by setting
the bits of DLCR3 corresponding to the status bits, bit 7 to 0.
Read
Write
Initial Value
Bit 7
PKT RDY
BIT CLR
0
Bit 6
BUS RD
ERR
BIT CLR
0
Bit 5
DMA
EOP
BIT CLR
0
Bit 4
RMT RST
BIT CLR
0
Bit 3
RX SRT
PKT
BIT CLR
0
Bit 2
Bit 1
Bit 0
ALG ERR CRC ERR OVRFLO
BIT CLR BIT CLR BIT CLR
0
0
0
Bit no. Bit name
7 PKT RDY
(Packet Ready)
6 BUS RD ERR
(Bus Read
Error)
5 DMA EOP
Operation
Read
Write
Read
Write
Read
Write
Value
0
1
0
1
0
1
0
1
0
1
0
1
Function
No received packet is in the receiver buffer.
Indicates packets from self office received normally and
transferred completely to receiver buffer.
In other words, at least one packet of receive data is in the
receiver buffer.
Not affected
This bit is cleared. If there are still received packets in the
receiver buffer even after the host system has read one
packet of receive data from the receiver buffer, this bit is
automatically reset.
No bus read error
Indicates LSI failed to assert RDY signal within 2.15 µs at
reading data in receiver buffer from host system.
In other words, the host system attempted to read data from
the receiver buffer, although the buffer has no data to read.
Not affected
This bit is cleared.
Indicates DMA transfer not yet
completed during DMA transfer.
This bit is cleared when both the
DMA RENA and DMA TENA bits of
the BMPR12 are cleared.
Indicates DMA transfer completed
and EOP signal asserted by
* : This bit is invalid in the
external DMA controller
PC card mode.
Not affected
This bit is cleared. This clearing
should be done by clearing both the
DMA RENA and DMA TENA bits of
the BMPR12.
(Continued)
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