MB86967 Datasheet, PDF (106/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(17)Burst DMA Access Timing
Parameter
Hold time for DREQ output
Hold time for DMACK input (from IOR, IOW negate)
Hold time for DREQ output
Hold time for DMACK input (from EOP/EOP negate)
Setup time for DMACK input
(VDD = +5 V ± 5%, GND = 0 V, Ta = 0°C to +70°C)
Value
Symbol
Unit
Min.
Typ.
Max.
t1
—
—
32
ns
t2
3
—
—
ns
t3
4
—
28
ns
t4
3
—
—
ns
t5
0
—
—
ns
• Burst DMA access timing (Exiting DMA from the MB86967)
DREQ
*1
*2
DMACK
IOR, IOW
t1
t1
t2
*1: This transition goes low at a single cycle before the last DMA when DLCR4 bit 2 is 1.
*2: This transition goes low at the last cycle of DMA when DLCR4 bit 2 is 0.
• Burst DMA access timing (When DMA is interrupted by DMACK input)
DREQ
DMACK
t5
t2
t1
t2
IOR, IOW
IOCHRDY*1
*2
*1: IOCHRDY signal timing is identical as that of bus timing.
*2: Interrupt period for DMA transfer
106