MB86967 Datasheet, PDF (40/129 Pages) Fujitsu Component Limited. – LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces

MB86967
(3) DLCR2: Transmit Interrupt Enable Register
The DLCR2 register enables a transmit interrupt. When the bit corresponding to the status bit of DLCR0 is set
to 1, the external interrupt INT is asserted when the status bit is set.
Read/Write
Initial Value
Bit 7
ENA
TMT OK
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
ENA
JABBER
0
Bit 2
ENA COL
0
Bit 1
ENA
16COL
0
Bit 0
ENA BUS
WR ERR
0
Bit no. Bit name
7 ENA TMT OK
6 to 4 Not used
3 ENA JABBER
2 ENA COL
1 ENA 16COL
0 ENA BUS RD
ERR
Operation
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Value
0
1
—
0
1
0
1
0
1
0
1
Function
Disables TMT OK interrupt
Enables TMT OK interrupt
The read value is always 0. Write 0 to these bits at writing.
Disables JABBER interrupt
Enables JABBER interrupt
Disables COL interrupt
Enables COL interrupt
Disables 16COL interrupt
Enables 16COL interrupt
Disables BUS RD ERR interrupt
Enables BUS RD ERR interrupt
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