MC9S08JM16 Datasheet, PDF (92/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTEDS7
0
6
PTEDS6
5
PTEDS5
4
PTEDS4
3
PTEDS3
2
PTEDS2
1
PTEDS1
0
0
0
0
0
0
Figure 6-26. Output Drive Strength Selection for Port E (PTEDS)
0
PTEDS0
0
Table 6-25. PTEDS Register Field Descriptions
Field
Description
7:0
PTEDS[7:0]
Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high
output drive for the associated PTE pin.
0 Low output drive enabled for port E bit n.
1 High output drive enabled for port E bit n.
6.5.11 Port F I/O Registers (PTFD and PTFDD)
Port F parallel I/O function is controlled by the registers listed below.
7
R
W
Reset
0
6
5
4
3
2
PTFD6
PTFD5
PTFD4
0
0
0
0
0
Figure 6-27. Port F Data Register (PTFD)
1
PTFD1
0
0
PTFD0
0
Table 6-26. PTFD Register Field Descriptions
Field
Description
6:4, 1:0
PTFD
[6:4, 1:0]
Port F Data Register Bits— For port F pins that are inputs, reads return the logic level on the pin. For port F
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08JM16 Series Data Sheet, Rev. 2
92
Freescale Semiconductor