MC9S08JM16 Datasheet, PDF (244/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (S08SPI16V1)
SPE
ENABLE
SPI SYSTEM
SPIMODE
LSBFE
Tx BUFFER (WRITE SPIxDH:SPIxDL)
SHIFT
OUT
SPI SHIFT REGISTER
SHIFT
IN
8 OR 16
BIT MODE
Rx BUFFER (READ SPIxDH:SPIxDL)
SHIFT
DIRECTION
SHIFT
CLOCK
Rx BUFFER Tx BUFFER
FULL
EMPTY
SPC0
BIDIROE
PIN CONTROL
M
S
M
S
MOSI
(MOMI)
MISO
(SISO)
BUS RATE
CLOCK
SPIBR
CLOCK GENERATOR
MSTR
MASTER/SLAVE
MODE SELECT
CLOCK
LOGIC
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
MODFEN
SSOE
M
S
MASTER/
SLAVE
16-BIT COMPARATOR
SPIxMH:SPIxML
16-BIT LATCH
SPMF
SPMIE
SPSCK
SS
SPRF
SPTEF
SPTIE
MODF
SPIE
Figure 15-4. SPI Module Block Diagram
SPI
INTERRUPT
REQUEST
15.2 External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
15.2.1 SPSCK — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
MC9S08JM16 Series Data Sheet, Rev. 2
244
Freescale Semiconductor