MC9S08JM16 Datasheet, PDF (311/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Field
1
EPSTALL
0
EPHSHK
4
EPCTLDIS
X
X
Universal Serial Bus Device Controller (S08USBV1)
Table 17-18. EPCTLn Field Descriptions (continued)
Description
Endpoint Stall — When set, this bit indicates that the endpoint is stalled. This bit has priority over all other
control bits in the endpoint control register, but is only valid if EPTXEN=1 or EPRXEN=1. Any access to this
endpoint will cause the USB module to return a STALL handshake. Once an endpoint is stalled it requires
intervention from the host controller.
0 Endpoint n is not stalled
1 Endpoint n is stalled
Endpoint Handshake — This bit determines if the endpoint will perform handshaking during a transaction
to the endpoint. This bit will generally be set unless the endpoint is isochronous.
0 No handshaking performed during a transaction to this endpoint (usually for isochronous endpoints)
1 Handshaking performed during a transaction to this endpoint
Table 17-19. Endpoint Enable/Direction Control
Bit Name
3
EPRXEN
0
2
EPTXEN
0
Endpoint Enable/Direction Control
Disable endpoint
0
1
Enable endpoint for IN(TX) transfers only
X
1
0
Enable endpoint for OUT(RX) transfers only
0
1
1
Enable endpoint for IN, OUT and SETUP transfers.
1
1
1
RESERVED
17.4 Functional Description
This section describes the functional behavior of the USB module. It documents data packet processing
for endpoint 0 and data endpoints, USB suspend and resume states, SOF token processing, reset conditions
and interrupts.
17.4.1 Block Descriptions
Figure 17-2 is the block diagram. The module’s sub-blocks and external signals are described in the
following sections. The module involves several major blocks — USB transceiver (XCVR), USB serial
interface engine (SIE), a 3.3 V regulator (VREG), endpoint buffer manager, shared RAM arbitration, USB
RAM and the SkyBlue gasket.
17.4.1.1 USB Serial Interface Engine (SIE)
The SIE is composed of two major functions: TX Logic and RX Logic. These major functions are
described below in more detail. The TX and RX logic are connected by a USB protocol engine which
manages packet flow to and from the USB module. The SIE is connected to the rest of the system via
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
311