MC9S08JM16 Datasheet, PDF (82/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
Table 6-5. PTASE Register Field Descriptions
Field
Description
5,0
PTADS[5,0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
6.5.3 Port B I/O Registers (PTBD and PTBDD)
Port B parallel I/O function is controlled by the registers listed below.
7
R
W
Reset
0
6
5
4
3
2
1
0
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
0
0
0
0
0
0
0
Figure 6-7. Port B Data Register (PTBD)
Table 6-6. PTBD Register Field Descriptions
Field
Description
5:0
PTBD[5:0]
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
R
W
Reset
0
6
5
4
3
2
PTBDD5
PTBDD4
PTBDD3
PTBDD2
0
0
0
0
0
Figure 6-8. Data Direction for Port B (PTBDD)
1
PTBDD1
0
0
PTBDD0
0
Table 6-7. PTBDD Register Field Descriptions
Field
Description
5:0
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBDD[5:0] PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
MC9S08JM16 Series Data Sheet, Rev. 2
82
Freescale Semiconductor