MC9S08JM16 Datasheet, PDF (194/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
• BDIV=00 (divide by 1), RDIV < 010
BDIV=01 (divide by 2), RDIV < 011
12.5 Initialization / Application Information
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
12.5.1 MCG Module Initialization Sequence
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in t_irefst microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL will acquire lock in t_{fll_lock} milliseconds.
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the MCGSC register,
and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
NOTE
The BDIV value must not be changed to divide-by-1 without first trimming
the internal reference. Failure to do so could result in the MCU running out
of specification.
12.5.1.1 Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see Figure 12-8). Reaching any of the other modes requires
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. Write to MCGC1 to select the clock mode.
— If entering FEE, set RDIV appropriately, clear the IREFS bit to switch to the external reference,
and leave the CLKS bits at %00 so that the output of the FLL is selected as the system clock
source.
— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS
bits to %10 so that the external reference clock is selected as the system clock source. The
RDIV bits must also be set appropriately here according to the external reference frequency
because although the FLL is bypassed, it is still on in FBE mode.
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
useful if the application will switch back and forth between internal and external modes. For
MC9S08JM16 Series Data Sheet, Rev. 2
194
Freescale Semiconductor