MC9S08JM16 Datasheet, PDF (81/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.5.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS)
In addition to the I/O control, port A pins are controlled by the registers listed below.
7
R
W
Reset
0
6
5
4
3
2
1
0
PTAPE5
PTAPE0
0
0
0
0
0
0
0
Figure 6-4. Internal Pullup Enable for Port A (PTAPE)
Table 6-3. PTADD Register Field Descriptions
Field
Description
5,0
PTAPE[5,0]
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
7
6
5
4
3
2
1
R
PTASE5
W
Reset
0
0
1
1
1
1
1
Figure 6-5. Output Slew Rate Control Enable for Port A (PTASE)
0
PTASE0
1
Table 6-4. PTASE Register Field Descriptions
Field
Description
5,0
PTASE[5,0]
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
7
R
W
Reset
0
6
5
4
3
2
1
PTADS5
0
0
0
0
0
0
Figure 6-6. Output Drive Strength Selection for Port A (PTASE)
0
PTADS0
0
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
81