MC9S08JM16 Datasheet, PDF (47/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Memory
LDHX
TXS
#RamLast+1
;point one past RAM
;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.6, “Security,” for a detailed
description of the security feature.
4.4 USB RAM
USB RAM is discussed in detail in Chapter 17, “Universal Serial Bus Device Controller (S08USBV1).”
4.5 Flash
Flash memory is used for program storage. In-circuit programming allows the operating program to be
loaded into the flash memory after final assembly of the application product. It is possible to program the
entire array through the single-wire background debug interface. Because no special voltages are needed
for flash erase and programming operations, in-application programming is also possible through other
software-controlled communication paths. For a more detailed discussion of in-circuit and in-application
programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor
document order number HCS08RMv1.
4.5.1 Features
Features of the flash memory include:
• Flash size
— MC9S08JM16 — 16, 384 bytes (32 pages of 512 bytes each)
— MC9S08JM8 — 8,192 bytes (16 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for flash and RAM
• Auto power-down for low-frequency read accesses
4.5.2 Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (f_FCLK) between 150 kHz and 200 kHz
(see Section 4.7.1, “Flash Clock Divider Register (FCDIV).”) This register can be written only once, so
normally this write is done during reset initialization. FCDIV cannot be written if the access error flag,
FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV
register. One period of the resulting clock (1/f_FCLK) is used by the command processor to time program
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
47