MC9S08JM16 Datasheet, PDF (64/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
UNSTACKING
ORDER
TOWARD LOWER ADDRESSES
7
0
51
42
33
24
15
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)*
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
SP AFTER
INTERRUPT STACKING
SP BEFORE
THE INTERRUPT
STACKING
ORDER
TOWARD HIGHER ADDRESSES
* High byte (H) of index register is not automatically stacked.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag must be cleared at the beginning of the ISR, so that if another interrupt is generated by
this same source, it will be registered to be serviced after completion of the current ISR.
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 for the IRQ pin to act as the interrupt request
(IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG),
whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an
interrupt or only sets the IRQF flag which can be polled by software.
MC9S08JM16 Series Data Sheet, Rev. 2
64
Freescale Semiconductor