MC9S08JM16 Datasheet, PDF (83/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.5.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS)
In addition to the I/O control, port B pins are controlled by the registers listed below.
7
R
W
Reset
0
6
5
4
3
2
PTBPE5
PTBPE4
PTBPE3
PTBPE2
0
0
0
0
0
Figure 6-9. Internal Pullup Enable for Port B (PTBPE)
1
PTBPE1
0
0
PTBPE0
0
Table 6-8. PTBPE Register Field Descriptions
Field
Description
5:0
PTBPE[5:0]
Internal Pullup Enable for Port B Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.
7
R
W
Reset
0
6
5
4
3
2
1
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
0
1
1
1
1
1
Figure 6-10. Output Slew Rate Control Enable (PTBSE)
0
PTBSE0
1
Table 6-9. PTBSE Register Field Descriptions
Field
Description
5:0
PTBSE[5:0]
Output Slew Rate Control Enable for Port B Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor
83