MC9S08JM16 Datasheet, PDF (150/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (S08ADC12V1)
10.4.4.5 Sample Time and Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock (f_ADCK).
After the module becomes active, sampling of the input begins. ADLSMP selects between short (3.5
ADCK cycles) and long (23.5 ADCK cycles) sample times.When sampling is complete, the converter is
isolated from the input channel and a successive approximation algorithm is performed to determine the
digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon
completion of the conversion algorithm.
If the bus frequency is less than the f_ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f_ADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 10-13.
Table 10-13. Total Conversion Time vs. Control Conditions
Conversion Type
ADICLK ADLSMP
Max Total Conversion Time
Single or first continuous 8-bit
0x, 10
0
20 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit
0x, 10
0
Single or first continuous 8-bit
0x, 10
1
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit or 12-bit
0x, 10
1
Single or first continuous 8-bit
11
0
Single or first continuous 10-bit or 12-bit
11
0
Single or first continuous 8-bit
11
1
Single or first continuous 10-bit or 12-bit
11
1
Subsequent continuous 8-bit;
f_BUS > f_ADCK
xx
0
Subsequent continuous 10-bit or 12-bit;
xx
0
f_BUS > f_ADCK
Subsequent continuous 8-bit;
f_BUS > f_ADCK/11
xx
1
Subsequent continuous 10-bit or 12-bit;
xx
1
f_BUS > f_ADCK/11
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
23 ADCK Cyc
Conversion time =
+
8 MHz/1
5 bus Cyc
8 MHz
= 3.5 μs
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
MC9S08JM16 Series Data Sheet, Rev. 2
150
Freescale Semiconductor