MC9S08JM16 Datasheet, PDF (362/386 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.11 MCG Specifications
Table A-11. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C
Rating
Symbol
Min.
Typical
Max.
Unit
1
P
Internal reference frequency — factory trimmed at V_DD
= 5 V and temperature = 25 °C
f_{int_ft}
—
31.25
—
kHz
2 P _{Average internal reference frequency — untrimmed}¹
f_{int_ut}
25
32.7
41.66
kHz
3 P Average internal reference frequency — user trimmed
f_{int_t}
31.25
—
39.0625 kHz
4 D Internal reference startup time
t_irefst
—
60
100
μs
5
—
DCO output frequency range — untrimmed¹
value provided for reference: f_{dco_ut} = 1024 X f_{int_ut}
f_{dco_ut}
25.6
33.48
42.66
MHz
6 P DCO output frequency range — trimmed
f_{dco_t}
32
—
40
MHz
7
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δf_{dco_res_t}
—
±0.1
±0.2
%f_dco
8
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Δf_{dco_res_t}
—
±0.2
±0.4
%f_dco
9
P
Total deviation of trimmed DCO output frequency over
voltage and temperature
Δf_{dco_t}
—
0.5
–1.0
±2
%f_dco
10
C
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0 – 70 °C
Δf_{dco_t}
—
± 0.5
±1
%f_dco
11 C _{FLL acquisition time}²
t_{fll_acquire}
—
—
1
ms
12 D _{PLL acquisition time}³
t_{pll_acquire}
—
—
1
ms
Long term Jitter of DCO output clock (averaged over
13 C _{2ms interval)4}
C_Jitter
—
0.02
0.2
%f_dco
14 D VCO operating frequency
f_vco
7.0
—
55.0
MHz
15 D PLL reference frequency range
f_{pll_ref}
1.0
—
2.0
MHz
16
T
Long term accuracy of PLL output clock (averaged over
2 ms)
f_{pll_jitter_2ms}
—
0.590⁵
—
%f_pll
17 T Jitter of PLL output clock measured over 625 ns
f_{pll_jitter_625ns}
—
0.566⁵
—
%f_pll
18 D _{Lock entry frequency tolerance} ⁶
D_lock
±1.49
—
±2.98
%
19 D _{Lock exit frequency tolerance} ⁷
D_unl
±4.47
—
±5.97
%
20 D Lock time — FLL
t_{fll_lock}
—
—
t_{fll_acquire +}
1075(1/^fint_t)
s
21 D Lock time — PLL
t_{pll_lock}
—
—
t_{pll_acquire +}
1075(1/^fpll_ref)
s
22
D
Loss of external clock minimum frequency —
RANGE = 0
f_{loc_low}
(3/5) × f_int
—
—
kHz
23
D
Loss of external clock minimum frequency —
RANGE = 1
f_{loc_high}
(16/5) × f_int
—
—
kHz
1 _{TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing}
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
MC9S08JM16 Series Data Sheet, Rev. 2
362
Freescale Semiconductor